Thin SrTiO3 film deposited on top of a doped Si substrate
Specifications:
- Size 5x5, 10x10, 15x15 mm² (other shapes available on request)
- Thickness 725 ± 25 μm
- Orientation (001) ± 0.5°
- Doping p-type
- Resistivity 1-30 Ωcm
- SrTiO3 layer 4.0 ± 0.2 nm
- Roughness 3 ± 2 Å
- Mosaicity 0.4°
- Max temp. 800°C
Use cases:
- Projects on oxide epitaxy with perovskites (ferroelectrics, multiferroics, colossal magnetoresistance, high-Tc superconductivity etc.)
- Larger surfaces possible compared to regular STO crystals
- Layer transfer (i.e., removing Si is easy, STO not)
- MEMS processes with oxides (fabrication of oxide membranes by underetching the Si substrate)
Ideal for:
Researchers / R&D departments interested in oxide epitaxy with pervoskites (ferroelectrics, multiferroics, colossal magnetoresistance, high-Tc superconductivity, …) seeking to
- Scale up their technology (i.e., integration with Si is the only way forward)
- Get larger surfaces than what is possible with STO crystals
- Produce MEMS (via underetching of Si)
- Transfer layers of STO
- Use doped Si as backside contact layer (usually Nb doping for STO)
References
- Strain-Engineered Metal-to-Insulator Transition and Orbital Polarization in Nickelate Superlattices Integrated on Silicon, B. Chen et al., Adv. Mater., 2004995 (2020)
- Integration of Single Oriented Oxide Superlattices on Silicon Using Various Template Techniques, B. Chen et al., ACS Appl. Mater. Interfaces, 12(38) 42925 (2020)
- Thermal-strain-engineered ferromagnetism of LaMnO3/SrTiO3 heterostructures grown on silicon, B. Chen et al., Physical Review Materials 4, 024406 (2020)
- Microstructure analysis of epitaxial BaTiO3 thin films on SrTiO3-buffered Si: Strain and dislocation density quantification using HRXRD methods, A.Borzì et al., Materialia, 14, 100953 (2020)
- Monolithically Integrated Microelectromechanical Systems for On-Chip Strain Engineering of Quantum Dots, Y. Zhang et al., Nano Lett., 16(9), 5785 (2016)
- Wafer level integration of epitaxial piezoelectric thin films for novel NEMS, MEMS and MOEMS applications, M. Dekkers et al., Informatics, Electronics and Microsystems: TechConnect Briefs (2017
